1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to a lateral double diffused metal oxide semiconductor (LDMOS) device and a method of fabricating such a device.
2. Description of the Prior Art
LDMOS devices are typically used in high voltage applications, and when designing such LDMOS devices, it is important that the device should have a very high breakdown voltage (Vbd), whilst also exhibiting, when operating, a low on-resistance (Ron). By designing LDMOS devices with low on-resistance and high breakdown voltage, such devices will typically exhibit low power loss in high voltage applications. In addition, by exhibiting a low on-resistance, a high drain current (Idsat) can be achieved when the transistor is in saturation. One problem when designing such LDMOS devices is that techniques and structures that tend to maximise Vbd tend to adversely affect the Ron and vice versa.
It is well known in the art to seek to increase the breakdown voltage by producing a field oxide (FOX) underlying a portion of the gate (this portion of the gate being referred to as the field plate), the FOX layer reducing electric field crowding at the gate edge. FIG. 1 is a cross-sectional view of such a conventional LDMOS device 100. As illustrated in FIG. 1, drain region 106 is formed within an N well 104 and source region 108 is formed within a P-substrate 102. A gate 110 is formed on the surface of the substrate, one portion of which is separated from the substrate by a thin insulating oxide layer. A FOX layer 112 is formed between the substrate 102 and a further portion of the gate 110. The FOX layer consumes silicon in the substrate as it is formed, the formation of the FOX layer typically being via a thermal oxidation process.
U.S. Pat. Nos. 6,448,625 B, 6,468,870 B, 6,531,355 B and 6,580,131 B illustrate various designs of MOS and LDMOS devices which incorporate such a FOX layer.
U.S. Pat. No. 6,441,431 B describes an LDMOS device in which a dielectric insulating layer is formed between the gate and the substrate having two portions of different thicknesses. The formation of this dielectric insulating layer with two different thickness portions is discussed at column 4 of that document. As discussed at column 4, lines 48 to 60, preferably both portions of the dielectric layer are comprised of the same material and are formed using a thermally grown silicon dioxide layer.
Whilst the prior art techniques such as those discussed above provide insulating layers which seek to increase the breakdown voltage of the device, it would be desirable to further improve the trade off between high breakdown voltage and reduced on-resistance. In particular it would be desirable to enable the on-resistance to be further reduced within a device exhibiting a particular breakdown voltage.